有些應(yīng)用中,需要降低Xilinx MPSoC的功耗。缺省設(shè)置中,R5/GPU都被使能。如果需要省電,可以在Vivado里關(guān)閉R5/GPU。步驟如下:
1.選中 MPSoC IP,在右鍵菜單中選擇Block Properties.
2.在窗口Block Properties中,選擇Properties.
3. 在窗口中,展開 “Config”.
4. 在搜索框中輸入 “Power”, 出現(xiàn)PSU_RPU_POWER_ON等選項(xiàng)。如果值是1,表示被使能;如果值是0,表示被關(guān)閉。如果要關(guān)閉,點(diǎn)擊最左邊的編輯圖標(biāo),輸入0。
編輯前Power選項(xiàng)
編輯后Power選項(xiàng)
在Vivado里編輯完成后,執(zhí)行“Generate Output Products”, 在導(dǎo)出Hardware的HDF/XSA文件。
2. JTAG檢查R5/A53狀態(tài)
在SDK/Vitis里創(chuàng)建FSBL和Standalone程序,啟動(dòng)后,在XSCT命令后窗口下,檢查R5/A53狀態(tài),可以看到設(shè)置為0的R5/A53的狀態(tài)是No Power。
xsct% connect
tcfchan#2
xsct% target
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (No Power)
7 Cortex-R5 #1 (No Power)
8 APU
9 Cortex-A53 #0 (Running)
10 Cortex-A53 #1 (Power On Reset)
11 Cortex-A53 #2 (No Power)
12 Cortex-A53 #3 (No Power)
3. 代碼
代碼在psu_init.c里的函數(shù)psu_peripherals_powerdwn_data( )里。
/*
POWER DOWN REQUEST INTERRUPT ENABLE
/
/
Register : REQ_PWRDWN_INT_EN @ 0XFFD80218
Power-down Request Interrupt Enable for Dual_R5
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU 1
Power-down Request Interrupt Enable for GPU PP0
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0 1
Power-down Request Interrupt Enable for GPU PP1
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1 1
Power-down Request Interrupt Enable for ACPU2
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2 1
Power-down Request Interrupt Enable for ACPU3
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3 1
Power-down Request Interrupt Enable Register. Writing a 1 to this locati
on will unmask the Interrupt.
(OFFSET, MASK, VALUE) (0XFFD80218, 0x0000043CU ,0x0000043CU)
/
PSU_Mask_Write(PMU_GLOBAL_REQ_PWRDWN_INT_EN_OFFSET,
0x0000043CU, 0x0000043CU);
/##################################################################### */
/*
POWER DOWN TRIGGER
/
/
Register : REQ_PWRDWN_TRIG @ 0XFFD80220
Power-down Request Trigger for Dual_R5
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU 1
Power-down Request Trigger for GPU PP0
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0 1
Power-down Request Trigger for GPU PP1
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1 1
Power-down Request Trigger for ACPU2
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2 1
Power-down Request Trigger for ACPU3
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3 1
Power-down Request Trigger Register. Writing a 1 to this location will t
rigger a power-down request to the PMU.
(OFFSET, MASK, VALUE) (0XFFD80220, 0x0000043CU ,0x0000043CU)
/
PSU_Mask_Write(PMU_GLOBAL_REQ_PWRDWN_TRIG_OFFSET,
0x0000043CU, 0x0000043CU);
/##################################################################### */
審核編輯 :李倩
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原文標(biāo)題:【干貨分享】 在Vivado里關(guān)閉R5/GPU,降低Xilinx MPSoC的功耗
文章出處:【微信號(hào):zhuyandz,微信公眾號(hào):FPGA之家】歡迎添加關(guān)注!文章轉(zhuǎn)載請(qǐng)注明出處。
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