（1）編dcm時(shí)鐘控制測試程序時(shí)，設(shè)置好了ip，例化輸出，綜合時(shí)出現(xiàn)錯(cuò)誤

ERROR:Xst:2035 - Port has illegal connections. This port is connected to an input buffer and other components.

查到的解決方法是禁掉自動(dòng)I/O Buffer insertion 功能，具體的做法是右擊synthesize，然后properties-》Xilinx Specific Options，把add I/O buffer 的勾去掉，綜合通過。但是這樣處理了之后在map時(shí)又引入了許多的warning，而且還會(huì)引發(fā)錯(cuò)誤。方法出處一會(huì)轉(zhuǎn)帖出來。

（2）dac8812的控制時(shí)序測試時(shí)，綜合沒問題，但是map時(shí)出現(xiàn)錯(cuò)誤

Pack:198 - NCD was not produced. All logic was removed from design.

其實(shí)這個(gè)錯(cuò)誤的來源是下面的這幾個(gè)warning導(dǎo)致

MapLib:701 - Signal clk connected to top level port clk has been removed.

MapLib:701 - Signal dad connected to top level port dad has been removed.

以下省略很多這樣的warning，這個(gè)問題之前一直沒注意，后來才知道問題出在我在問題（1）中的處理，按照同樣的流程把a(bǔ)dd I/O buffer 勾上，綜合到route都沒什么問題，可見warning也是不能忽略的呀。

（3）剛才不知道怎么了，行為仿真的時(shí)候出現(xiàn)下面的error

ERROR:HDLParsers:3482 - Could not resolve instantiated unit dacinter in Verilog module work/datest_top in any library

意思好像是找不到我top里例化的模塊了，重新添加了一下，好用了。

（4）行為仿真發(fā)現(xiàn)沒有波形，全是XX或者ZZZ，以前改一下clk頻率就好了，這回這招不好使了，后來嘗試改了一下rst的時(shí)間點(diǎn)，向后一段時(shí)間，發(fā)現(xiàn)好用了，仿真用的是ise自帶的simulation。

（5）綜合錯(cuò)誤：ERROR:Xst:528 - Multi-source in Unit on signal

大多數(shù)時(shí)候應(yīng)該是同一個(gè)變量，在兩個(gè)always模塊中賦值了。還查到一些其他情況，一并粘貼：

Solution 1

This error appears when XST determines that there is contention on a particular signal. If the processes assigning values to this signal are mutually exclusive （as in the case of 3-state buffers）， this message can be ignored.

However， in most cases， XST is able to determine when multiple drivers are illegal， and will stop synthesis soon after this message.

Check this signal and modify your code to avoid the existing contention.

Solution 2

In some cases， XST ties unconnected output ports to ground. If the output port is part of a 3-state bus， which in turn connects to another 3-state bus， then connecting one bit of the bus to ground will cause a multiple-driver error. Verify that this is not occurring in your design by searching for the following warning：

“WARNING:Xst:1305 - Output 》 is never assigned. Tied to value 0.”

To work around this issue， remove the unused output port.

Solution 3

This has also been seen in the following condition：

When there is an association signal named to_qvm_d4.Q_num.

When using association signal（to_qvm_d4.Q_num）， XST will rename it to “to_qvm_d4_Q_num” during synthesis. There is signal named “to_qvm_d4_Q_num” in the same architecture. XST is confused with these two signals and errors.

To work around this issue， rename either of the two signals.

Solution 4

EDK Designs

For EDK Designs using bidirectional signals DIR=IO and THREE_STATE=FALSE， the external port name must match the connecting signal name exactly. NOTE： IOB_STATE is deprecated in future EDK versions.

（6）ERROR:Xst:902 - “dec_seg.v” line 38： Unexpected event in always block sensitivity list.

一個(gè)組合電路，綜合出錯(cuò)，上網(wǎng)查說是敏感表中不能既有電平又有邊沿，而且也不能同一個(gè)信號(hào)的上升沿和下降沿同時(shí)出現(xiàn)，去掉敏感表中的邊沿，運(yùn)行OK了。

（7）map的時(shí)候出現(xiàn)錯(cuò)誤ERROR:Pack:679 - Unable to obey design constraints （LOC = 。..） which require the combination of the following symbols into a single slice component：

檢查ucf文件，發(fā)現(xiàn)有一個(gè)管腳被重復(fù)分配，改了一下，運(yùn)行OK！

（8）ERROR:NgdBuild:604 - ‘GTP_DUAL_1’ could not be resolved，這個(gè)錯(cuò)誤在translate的時(shí)候報(bào)，是軟件的bug，網(wǎng)上查說ise12.2多發(fā)，但是我用的9.1也出了這個(gè)，原因大概是ISE只復(fù)制了頂層的NGC文件，即mycpu.ngc，而頂層mycpu還包含其它ngc文件，因此找不到，報(bào)錯(cuò)。按照查到的解決辦法，有兩種。

解決辦法1是：在mycpu module前面加上

（* box_type = “user_black_box” *）

如：

（* box_type = “user_black_box” *）

mycpu my_cpu_moudle （.fpga_0_clk_1_sys_clk_pin（sys_clk），

.fpga_0_rst_1_sys_rst_pin（sys_rst_n），

.fpga_0_RS232_RX_pin（uart_rxd），

.fpga_0_RS232_TX_pin（uart_txd），

.led_out_GPIO_IO_O_pin（led_out［0:3］））;

辦法2是在ISE 的processes欄下，選中Translate，右鍵process propreties.。..。

彈出Translate Properties對(duì)話框，

在-sd macro search path 中加上EDK工程的implementation子目錄的路徑就可以了

一開始采用了第一種解決方案，translate通過，但在map時(shí)出錯(cuò)。改用第二種，問題是，我用了兩個(gè)ip core，這個(gè)指定的路徑只能是一個(gè)最直接的目錄，所以只能完全解決其中一個(gè)core的錯(cuò)誤，把兩個(gè)core的文件夾里的文件全拷到工程目錄中，指定工程目錄路徑為implementation子目錄路徑，搞定。

可以忽略的warning

（1）ProjectMgmt - “F:/verilogworks/FPGATESTS/datest_top_map.ncd” line 0 duplicate design unit： ‘Module|datest_top’