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SM320VC5507-EP 增強型產品定點數字信號處理器

數據:

描述

The SM320VC5507 fixed-point digital signal processor (DSP) is based on the SMS320C55x DSP generation CPU processor core. The C55x? DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5507 is supported by the industry?s award-winning eXpressDSP?, Code Composer Studio? Integrated Development Environment (IDE), DSP/BIOS?, Texas Instruments? algorithm standard, and the industry?s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX?, XDS510? emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

特性

  • 高性能,低功耗,定點
    SMS320C5507數字信號處理器
    • 9.26-,6.95- ,5 ns指令周期時間
    • 108,144,200 MHz時鐘頻率
    • 每個周期執行一/兩條指令
    • Dual乘法器(高達4億 - 每秒累加(MMACS))
    • 兩個算術/邏輯單元(ALU)
    • 三個內部數據/操作數讀取總線
      和兩個內部數據/操作數寫總線
  • 64K x 16位片上RAM,??由以下部分組成:
    • 64K字節的雙存取RAM( DARAM)8
      4K x 16位塊
    • 64K字節的單訪問RAM(SARAM)8
      4K x 16位塊
    < /li>
  • 64K字節的單等待狀態片上ROM
    (32K x 16位)
  • 8M x 16位最大可尋址外部存儲空間(同步) DRAM)
  • 16位外部并行總線存儲器
    支持:
    • 帶GPIO的外部存儲器接口(EMIF)
      功能和Gluel ess接口:
      • 異步靜態RAM(SRAM)
      • 異步EPROM
      • 同步DRAM(SDRAM)
    • < li>具有GPIO功能的16位并行增強型主機端口接口(EHPI)
  • 六個設備功能域的可編程低功耗控制
  • 基于片上掃描的仿真邏輯
  • 片上外設
    • 兩個20位定時器
    • 看門狗定時器
    • 六通道直接存儲器訪問(DMA)控制器
    • 三個多通道緩沖串行端口(McBSP)
    • 可編程鎖相環時鐘發生器
    • 七(LQFP) )或八個(BGA)通用I /O(GPIO)
      引腳和通用輸出引腳(XF)
    • USB全速(12 Mbps)從端口支持批量,< br>中斷和同步傳輸
    • 內部集成電路(I 2 C)多主機和從機接口
    • 實時時鐘( RTC)具有晶體輸入,獨立時鐘
      域,獨立電源y
    • 4通道(BGA)或2通道(LQFP)10位
      逐次逼近A /D
  • IEEE Std 1149.1 (1)(JTAG)邊界掃描邏輯
  • 封裝:
    • 144端子薄型四方扁平封裝(LQFP)
      (PGE后綴)< /li>
  • 1.2-V內核(108 MHz),2.7 V? 3.6V I /O
  • 1.35-V內核(144 MHz),2.7 V? 3.6V I /O
  • 1.6V內核(200 MHz),2.7 V? 3.6-VI /Os
  • 支持國防,航空和醫療應用
    • 受控基線
    • 一個裝配/測試現場
    • 一個制造現場
    • 軍用(?? 55°C /125°C)溫度范圍(2)
    • 延長產品生命周期
    • 擴展產品變更通知
    • 產品可追溯性

(1) IEEE標準1149.1 -1990標準測試訪問端口和邊界掃描架構。
(2)可提供更多溫度范圍 - 聯系工廠
C55x,eXpressDSP,Code Composer Studio,DSP /BIOS,RTDX,XDS510,TMS320,TMS320C5000,TMS320C55x,TMS320C55x是商標德州儀器。

參數 與其它產品相比?C5000 DSP

?
Applications
Operating Systems
DSP
DSP MHz
DRAM
Operating Temperature Range (C)
SPI
I2C
Rating
SM320VC5507-EP
Audio
Automotive
Communications and Telecom
Industrial ? ?
DSP/BIOS
VLX ? ?
1 C55x ? ?
108
144
200 ? ?
SDRAM ? ?
-55 to 85 ? ?
0 ? ?
1 ? ?
HiRel Enhanced Product ? ?

技術文檔

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