由于系統時鐘頻率和上升時間的增長，信號完整性設計變得越來越重要。不幸的是，絕
大多數數字電路設計者并沒意識到信號完整性問題的重要性，或者是直到設計的最后階段才初步認識到。
本篇介紹了高速數字硬件電路設計中信號完整性在通常設計的影響。這包括特征阻抗控
制、終端匹配、電源和地平面、信號布線和串擾等問題。掌握這些知識，對一個數字電路設計者而言，可以在電路設計的早期，就注意到潛在可能的信號完整性問題，還可以幫助設計則在設計中盡量避免信號完整性對設計性能的影響。
As system clock frequencies and rise times increase, signal integrity design considerations are
becoming ever more important. Unfortunately many Digital Designers may not recognize the
importance of signal integrity issues and problems may not be identified until it is too late.
This paper presents the most common design issues affecting signal integrity in high-speed digital hardware design. These include impedance control, terminations, ground/power planes, signal routing and crosstalk. Armed with the knowledge presented here, a digital designer will be able to recognize potential signal integrity problems at the earliest design stage. Also, the designer will be able to apply techniques presented in this paper to prevent these issues affecting the performance of their design.