集成鎖相環(huán)提供更高的頻率性能，提高用戶的利益

　　鎖相環(huán)（PLL）是電子系統(tǒng)中最通用，靈活和有價(jià)值的電路配置之一，導(dǎo)致其在許多應(yīng)用中的應(yīng)用。它是用于時(shí)鐘同步和恢復(fù)，作為頻率合成器，并作為一個(gè)可調(diào)諧振蕩器，僅舉幾個(gè)例子。其結(jié)果是，PLL被發(fā)現(xiàn)在許多射頻設(shè)備項(xiàng)目，包括無(wú)線電接收機(jī)和測(cè)試設(shè)備。根據(jù)其具體實(shí)施，它可以從近DC到GHz和更高的頻率，實(shí)現(xiàn)了系統(tǒng)和電路中的許多關(guān)鍵角色。

　　PLL是一個(gè)閉環(huán)（負(fù)反饋）架構(gòu)，基本鎖相環(huán)由這些塊組成（圖1）：

　　Figure 1： A basic PLL is a closed-loop， negative feedback system where the error between a reference signal and the VCO output is used to correct that output; the low-pass filter is a critical element in establishing the loop’s dynamics.

　　A phase/frequency detector （PFD） （often simply called a phase-detector PD） compares an input signal to a reference signal and produces an error signal which is proportional to their phase difference （keep in mind that phase and frequency are intimately related， as frequency is the time derivative of phase）; the phase-detector output usually goes to a charge pump which transforms the small current difference into a larger voltage

　　A low-pass filter （LPF）， which shapes the spectrum of the error signal; the design of this filter is often a combination of engineering science and intuitive art， and is a major factor in setting many of the dynamics of PLL operation

　　A voltage-controlled oscillator （VCO） with output phase/frequency controlled by the error signal

　　An optional frequency divider at the VCO output， which causes the PLL to generate frequencies at a multiple factor N of the reference frequency; N can be an integer， and many PLL designs support fractional-N non-integer division