資料介紹
1.0 INTRODUCTION 1
2.0 MEMORY ORGANIZATION? 2
2.1 Program Memory 2
2.2 Data Memory 2
3.0 SPECIAL FUNCTION
REGISTERS? 4
4.0 PORT STRUCTURES AND
OPERATION? 10
4.1 I/O Configurations 10
4.2 Port 1 and Port 3 10
4.3 Port 0 and Port 2 10
4.4 Read-Modify-Write Instructions 13
4.5 Quasi-Bidirectional Port
Operation 13
4.6 Port Loading 14
4.7 Accessing External Memory? 15
4.7.1 Bus Cycle Definition 17
4.7.2 External Bus Cycles with Wait
States 21
4.7.3 Port 0 and Port 2 for States in
Non-Page and Page Mode? 22
5.0 TIMERS/COUNTERS 23
5.1 TIMER 0 AND TIMER 1 23
5.2 TIMER 2? 26
6.0 PROGRAMMABLE COUNTER
ARRAY? 30
6.1 PCA 16-Bit Timer/Counter? 32
6.2 Capture/Compare Modules 34
6.3 16-Bit Capture Mode 37
6.4 16-Bit Software Timer Mode? 37
6.5 High Speed Output Mode 38
6.6 Watchdog Timer Mode 38
6.7 Pulse Width Modulator Mode 39
7.0 SERIAL INTERFACE 41
7.1 Framing Error Detection? 42
7.2 Multiprocessor Communications? 42
7.3 Automatic Address Recognition? 42
7.4 Baud Rates 44
7.5 Using Timer 1 to Generate Baud
Rates? 44
7.6 Using Timer 2 to Generate Baud
Rates? 45
8.0 WATCHDOG TIMER 46
8.1 Using the WDT 46
8.2 WDT during Idle Mode and
Powerdown 46
9.0 INTERRUPTS 47
9.1 External Interrupts 47
9.2 Timer Interrupts 49
9.3 PCA Interrupt 50
9.4 Serial Port Interrupt 50
9.5 Interrupt Enable 50
9.6 Interrupt Priorities 51
9.7 Interrupt Processing 54
9.7.1 Minimum Fixed Interrupt
Time 55
9.7.2 Variable Interrupt
Parameter 55
9.7.3 Response Time Variables? 55
9.7.4 Computation of Worst-Case
Latency With Variables? 56
9.7.5 Blocking Conditions 57
9.7.6 Interrupt Vector Cycle 57
9.7.7 ISRs in Process 58
10.0 RESET 58
10.1 Externally Initiated Resets 58
10.2 WDT Initiated Resets 59
10.3 Reset Operation 59
10.4 Power-on Reset 59
11.0 POWER-SAVING MODES OF
OPERATION? 60
11.1 Idle Mode 60
12.0 PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY 62
12.1 Programming and Verifying
Modes? 62
12.2 Lock Bit System 64
12.3 Encryption Array 64
12.4 Signature Bytes 64
13.0 ON-CIRCUIT EMULATION (ONCE)
MODE? 65
14.0 ON-CHIP OSCILLATOR 66
15.0 INSTRUCTION SET
REFERENCE? 68
2.0 MEMORY ORGANIZATION? 2
2.1 Program Memory 2
2.2 Data Memory 2
3.0 SPECIAL FUNCTION
REGISTERS? 4
4.0 PORT STRUCTURES AND
OPERATION? 10
4.1 I/O Configurations 10
4.2 Port 1 and Port 3 10
4.3 Port 0 and Port 2 10
4.4 Read-Modify-Write Instructions 13
4.5 Quasi-Bidirectional Port
Operation 13
4.6 Port Loading 14
4.7 Accessing External Memory? 15
4.7.1 Bus Cycle Definition 17
4.7.2 External Bus Cycles with Wait
States 21
4.7.3 Port 0 and Port 2 for States in
Non-Page and Page Mode? 22
5.0 TIMERS/COUNTERS 23
5.1 TIMER 0 AND TIMER 1 23
5.2 TIMER 2? 26
6.0 PROGRAMMABLE COUNTER
ARRAY? 30
6.1 PCA 16-Bit Timer/Counter? 32
6.2 Capture/Compare Modules 34
6.3 16-Bit Capture Mode 37
6.4 16-Bit Software Timer Mode? 37
6.5 High Speed Output Mode 38
6.6 Watchdog Timer Mode 38
6.7 Pulse Width Modulator Mode 39
7.0 SERIAL INTERFACE 41
7.1 Framing Error Detection? 42
7.2 Multiprocessor Communications? 42
7.3 Automatic Address Recognition? 42
7.4 Baud Rates 44
7.5 Using Timer 1 to Generate Baud
Rates? 44
7.6 Using Timer 2 to Generate Baud
Rates? 45
8.0 WATCHDOG TIMER 46
8.1 Using the WDT 46
8.2 WDT during Idle Mode and
Powerdown 46
9.0 INTERRUPTS 47
9.1 External Interrupts 47
9.2 Timer Interrupts 49
9.3 PCA Interrupt 50
9.4 Serial Port Interrupt 50
9.5 Interrupt Enable 50
9.6 Interrupt Priorities 51
9.7 Interrupt Processing 54
9.7.1 Minimum Fixed Interrupt
Time 55
9.7.2 Variable Interrupt
Parameter 55
9.7.3 Response Time Variables? 55
9.7.4 Computation of Worst-Case
Latency With Variables? 56
9.7.5 Blocking Conditions 57
9.7.6 Interrupt Vector Cycle 57
9.7.7 ISRs in Process 58
10.0 RESET 58
10.1 Externally Initiated Resets 58
10.2 WDT Initiated Resets 59
10.3 Reset Operation 59
10.4 Power-on Reset 59
11.0 POWER-SAVING MODES OF
OPERATION? 60
11.1 Idle Mode 60
12.0 PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY 62
12.1 Programming and Verifying
Modes? 62
12.2 Lock Bit System 64
12.3 Encryption Array 64
12.4 Signature Bytes 64
13.0 ON-CIRCUIT EMULATION (ONCE)
MODE? 65
14.0 ON-CHIP OSCILLATOR 66
15.0 INSTRUCTION SET
REFERENCE? 68
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