sv2v:從SystemVerilog到Verilog , sv2v將SystemVerilog (IEEE 1800-2017)轉換為Verilog (IEEE 1364-2005)， 重點是支持了可合成的語言結構。

其主要目標是創建一個完全免費和開放源碼的工具，用于將SystemVerilog轉換為Verilog。雖然執行這種轉換的方法已經存在，但它們通常要么依賴于商業工具，要么受到范圍的限制。

用法

sv2v [OPTIONS] [FILES]

Preprocessing:
  -I --incdir=DIR           Add directory to include search path
  -D --define=NAME[=VALUE]  Define a macro for preprocessing
     --siloed               Lex input files separately, so macros from
                            earlier files are not defined in later files
     --skip-preprocessor    Disable preprocessor
Conversion:
  -E --exclude=CONV         Exclude a particular conversion (always, assert,
                            interface, or logic)
  -v --verbose              Retain certain conversion artifacts
  -w --write=MODE           How to write output; default is 'stdout'; use
                            'adjacent' to create a .v file next to each input
Other:
     --help                 Display help message
     --version              Print version information
     --numeric-version      Print just the version number