以 IP(Intellectual Property )核復(fù)用為基礎(chǔ)的SoC（System on a Chip，簡稱SoC）設(shè)計是以軟硬件協(xié)同設(shè)計為主要設(shè)計方法的芯片設(shè)計技術(shù)。本文從IP 核復(fù)用技術(shù)、軟硬件
協(xié)同設(shè)計技術(shù)兩個方面探討了SoC 設(shè)計中的關(guān)鍵技術(shù)。其中以O(shè)CP 及Wishbone 總線為例，總結(jié)了片上總線的特點及其接口技術(shù)，討論了IP 核復(fù)用技術(shù)的應(yīng)用方法及優(yōu)勢；通過與傳統(tǒng)的IC 設(shè)計相比較，描述了軟硬件協(xié)同設(shè)計的流程特征，并探討了軟硬件協(xié)同仿真技術(shù)，同時其發(fā)展趨勢作了展望。
[關(guān)鍵詞]SoC：IP 復(fù)用：協(xié)同設(shè)計：驗證；技術(shù)
[Abstract] The main design method of SoC technology based on IP(Intellectual
Property) core reuse technology is hardware and software co-design technology. The
paper discussed the critical technologies of SoC design, they include IP reuse
technology and co-design technology. The characteristics and connection technology
of SoC bus are summed with an example of Wishbone Bus. Comparing with the traditional
IC design method, design flow of software/hardware co-design is also discussed, The
problems of research in the future are as well analyzed in this paper.
[Key words] SoC: IP reuse: co-design : Verification: Technology